Intel Lakefield SOC With Foveros 3D Packaging Previewed

By March 2, 2019 NEWS
Intel Lakefield SOC With Foveros 3D Packaging Previewed

Intel has revealed some interesting details about their upcoming Lakefield SOC which utilizes the Foveros 3D packaging technology. The new SOC will be the first from Intel utilizing 3D integration that will allow for much smaller chip packages which will help create a range of new platforms and PC form factors.

3D chip stacking has long held promise as a meaningful method of advancing silicon performance, but progress in the field has been slow, to say the least. For one thing, CPUs have a nasty tendency to overheat if you stack cores on top of them. Validation has also been a slow, careful process. But at its Tech Day this week, Intel revealed a new technology for connecting components and creating a 3D chip architecture. Codenamed Foveros (a Greek word said to mean fierce or amazing, though I had trouble finding the definition), this new 3D chip-stacking method could revolutionize product designs in the long term. Intel believes it can solve the problems that affect 3D CPU scaling and avoid the thermal issues that can kill these designs.

The chip Intel demoed today was a Foveros-enabled part with a Core CPU and Atom CPU sharing the same physical silicon. If you’re wondering how already in-market capabilities like EMIB compared to Foveros, the answer is that Foveros is a 3D chip stacking solution, while EMIB is designed for 2D stack solutions. The two technologies are not exclusive and we heard word that Intel was planning hardware that would utilize both.

Foveros-3

As far as what an actual implementation might look like, the block diagram below shows two separate chips mounted to the same package, via an active interposer layer.

This approach could give Intel tremendous flexibility when it comes to designing parts — a fact the company has already revealed to the public. At the request of a customer, Intel built a CPU with both an Atom and a standard Core processor onboard. This kind of heterogeneous combination has been done before, of course — ARM’s big.Little speaks for itself — but this is the first time we’ve seen it in an Intel CPU. The comparison against big.Little, while obvious, isn’t a particularly good one. Foveros is designed to integrate with a huge range of products and in many different capacities, while big.Little was a specific product implementation intended to reduce power consumption.

The final result of this product is a hybrid x86 architecture that can switch between Core and Atom, both of which are built on 10nm. Logic on the die is contained in the bottom chip, while the CPU cores reside up top. Both AMD and Intel are moving to chiplets, but Intel seems to believe doing them in 3D will allow them to gain additional ground. This unnamed part should launch in 2019 as well.

The combined capabilities of EMIB and Foveros give Intel significant reach and flexibility for wiring up hardware in new and interesting combinations. It’s no accident that we’re seeing AMD reaching for chiplets at the same time. More than three years ago, we wrote an article on Moore’s law, noting that the definition had changed over time as new problems presented themselves. Today, continuing with Moore’s law means continuing to improve scaling, integration, and power consumption. It’s an efficiency game. If Intel can actually start scaling 3D chip production, it could reshape how we design cores in the future.

Intel Lakefield SOC with Foveros 3D Packaging Previewed – 10nm Hybrid CPU Architecture, Gen 11 Graphics, Multiple Dies Stacked on Top of Each Other

Intel Lakefield is based around Foveros technology which helps connect chips and chiplets in a single package that matches the functionality and performance of a monolithic SOC. Each die is then stacked using FTF micro-bumps on the active interposer through which TSVs are drilled to connect with solder bumps and eventually the final package. The whole SOC is just 12×12 (mm) which is 144mm2.

At CES 2019, Intel previewed a new client platform, code-named “Lakefield,” featuring the first iteration of its new innovative Foveros 3D packaging technology. This hybrid CPU architecture enables combining different pieces of IP that might have previously been discrete into a single product with a smaller motherboard footprint, which allows OEMs more flexibility for thin and light form factor design. Lakefield is expected to be in production this year.

(Credit: Intel Corporation)

Talking about the SOC itself and its individual layers, the Lakefield SOC that has been previewed consists of at least four layers or dies, each serving a different purpose. The top two layers are composed of the DRAM which will supplement the processor as the main system memory. This is done through the PoP (Package on Package) memory layout which stacks two BGA DRAMs on top of each other as illustrated in the preview video. The SOC won’t have to rely on socketed DRAM in this case which saves a lot of footprint on the main board.

The second layer is the Compute Chiplet with a Hybrid CPU architecture and graphics, based on the 10nm process node. The Hybrid CPU architecture has a total of five individual Cores, one of them is labeled as the Big Core which features the Sunny Cove architecture. That’s the same CPU architecture that will be featured on Intel’s upcoming 10nm Ice Lake processors. The Sunny Cove Core is optimized for high-performance throughput. There are also four small CPUs that are based on the 10nm process but optimized for power efficiency.

The same die consists of Intel’s Gen 11 graphics engine with 64 Execution Units. Last week, we got to see the performance of an Intel GT2 (Gen 11) Iris Plus 940 graphics chip with 64 Execution Units and the results were quite good compared to existing Intel Gen 9.5 graphics chips. You can check out the performance results here.

Knowing that the Lakefield SOC will feature the same graphics engine, we can expect a very decent graphics performance out of this 3D stacked processor. Then last of all is the base die which serves as the cache and I/O block of the SOC. Labeled as the P1222 and based on a 22FFL process node, the base die comes with a low cost and low leakage design while providing a feature-rich array of I/O capabilities.

Given the extremely tiny chip size and the resultant smaller board sizes, Intel expects Forveros and Lakefield to unleash a wave of new, uncompromised PC devices, platforms and a range of an entirely new class of device in the coming years. Surely, Lakefield SOCs will be the first 3D design for a compute heavy and power efficient SOC and we would really like Intel to share some power and performance numbers of their upcoming SOC which is expected to go into production this year.

Intel Foveros 3D Packaging Technology Presentation (Intel Architecture Day 2018)

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